Class-D amplifiers are becoming increasingly popular due to their high efficiency (typically 90% or higher) and compact size. Such amplifiers are based on the PWM principle, and require input PWM signals to operate.
FIG. 1 is a schematic diagram of a device 10 for generating PWM signals.
A signal X is received at an input. The input signal X is to be converted into a PWM signal, but can take any form itself. In the illustrated example, X is a digital signal and has a high number of bits, such as 24. The input signal X is fed to an add/subtract unit 12, where it is combined with a feedback signal provided by a noise-shaping loop 18. The signal output from the add/subtract unit 12 is thus compensated for any error in the output of the device 10.
The compensated signal is passed to a loop filter 14, which can be implemented in many different ways. In one example, the loop filter 14 comprises one or more integrators, and these integrators can be arranged in one or multiple stages. The output of the loop filter 14 is provided to a PWM modulator 16. In FIG. 1, this is implemented by a simple comparator, although more complicated arrangements are also possible. The comparator compares the output of the loop filter 14 with a carrier signal, and outputs a 1-bit signal indicative of the comparison. The carrier signal can be a triangular wave signal or a saw-tooth signal, for example. Provided the output of the loop filter 14 varies at a lower rate than the carrier signal (which will be the case for all practical realisations), the output of the comparator switches only twice for each switching period of the carrier signal, thus generating a pulse of variable width in each period. This PWM signal Y is provided as an output of the device 10.
The PWM modulator 16 introduces a source of noise due to the quantization of the signal; for the device 10 to be used in an audio application, such noise has to be shaped so as not to fall within frequencies which can be heard by users. A noise-shaping feedback loop 18 is thus coupled around the PWM modulator 16, schematically illustrated between an output of the PWM modulator 16 and the add/subtract unit 12. Those skilled in the art will appreciate that the feedback signal Y may be multiplied by one or more coefficients and also combined with the input signal at one or more places in the processing chain in order to control precisely the effect of the noise-shaping loop 18.
The quality in the output signal Y can be increased by increasing the frequency fw with which the PWM modulator 16 is clocked. That is, for each period 1/fw, the PWM modulator 16 compares its two input signals and generates an output signal. In a typical audio application, for example, fw may be 40 MHz or higher, while the frequency of the carrier signal may be 200 kHz or higher. Typically, therefore, the PWM modulator 16 is clocked at a frequency fw which is approximately two orders of magnitude higher than the carrier frequency.
FIG. 2 is a schematic graph showing the waveforms of various signals in the PWM modulating device 10. The output of the loop filter 14 is illustrated by the curved solid line 200. This is illustrated as an analogue signal, but in practice also represents a digital signal with a high number of bits (e.g. 24, as in FIG. 1). The output of the loop filter 14 is illustrated as a continuous-time signal, but in practice may also represent a discrete-time signal with sampling frequency fw. The carrier signal is illustrated by the dashed line 202, and in this case is a rising sawtooth signal. As with the output of the loop filter 200, the carrier signal 202 may also be quantised in amplitude and in continuous-time or discrete-time with sampling frequency fw. The vertical dotted lines illustrate the sampling points of the PWM modulator 16. The output of the PWM modulator 16 (i.e. the PWM signal) is illustrated by the single-bit signal 204. Note that the amplitude of the PWM signal is illustrated at a lower level in order to differentiate it from the other signals in the graph. The PWM signal is described as having two possible states, “high” and “low”. These correspond to “0” and “1” logic signals, or “+1” and “−1” arithmetic signals. Note also that, in practice, the output of the loop filter 14 would vary far more slowly than indicated in the graph.
Initially, the output of the loop filter 200 is greater than the carrier signal 202 and thus the output of the PWM modulator 204 is high. At some point within the first switching period, the carrier signal 202 reaches an amplitude which is greater than the output of the loop filter 200 and the PWM modulator output 204 reverts to a low level. Because the PWM modulator 16 has a finite, albeit high, sampling frequency, the switch to a low logic output occurs at a time which is after the true point of intersection between the carrier signal and the loop filter output, if they were reconstructed as continuous-time signals based on available samples. This introduces a source of noise to the PWM signal and, in order to generate a higher quality output signal, the sampling frequency of the PWM modulator fw should be as high as possible.
In order to operate correctly, the noise-shaping loop 18 must also be clocked at the same high frequency fw as the PWM modulator 16. This means that the add/subtract unit 12 as well as the potentially significant amount of arithmetic logic (e.g. integrators, multipliers, etc) in the loop 18 and the loop filter 14 must all be clocked at fw. From a practical perspective this is likely to cause difficulties in synchronizing the hardware correctly, and of course results in higher power consumption generally.